1. Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) chips in general, and in particular to an integrated method of forming interconnect layers using low dielectric constant materials.
2. Description of the Prior Art
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings are also formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropic etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for conductive lines in the upper half of the insulating material, the vias openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. The following description will explain the various steps of one conventional method for forming dual damascene structure by reference FIGS. 1.
In the manufacture of a conventional dual damascene structure, a substrate 100 has a metal layer 120 formed therein as shown in FIG. 1A. An inter-metal dielectric layer 130 and a stop layer 132 are sequentially deposited on the substrate 100. A via hole pattern 150 is transferred into the stop layer 132, as shown in FIG. 1B. Then, another inter-metal dielectric layer 134 is coated on the stop layer 132, as shown in FIG. 1C. A trench line pattern 152 is transferred into the inter-metal dielectric layer 134 while the via hole pattern 150 is transferred into the inter-metal dielectric layer 130 using stop layer 132 as a mask, as shown in FIG. 1D. Then, a metal layer 160, such as tungsten or copper, is deposited to fill the via hole and trench line, as shown in FIG. 1E. The dual damascene structure is completed by using chemical mechanical polishing method to remove excess metal layer, as shown in FIG. 1F.
For 0.18 um process and beyond, dual damascene process is a key technology to push the design rule its limits, but it is difficult to control the process window especially in via and metal trench formation. Thus, good resolution of lithography (misalignment issue) and high selectivity of via etching is the key issue for back end interconnection.
On the other hand, low-dielectric constant materials are dedicated to combine with copper integration with damascene process. Thus a method of intergrating copper with low-dielectric constant materials is a very promising topic for future back end integration.